1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more specifically to a semiconductor integrated circuit device having a configuration for pseudo-tuning an internal power-supply voltage.
2. Description of the Background Art
Because of the influence of process variation and the like, an internal power-supply voltage of a device after the completion of a wafer process does not take a desired value. Thus, there is a need to tune the internal power-supply voltage before the actual use.
A power-supply tuning circuit 900 provided in a conventional semiconductor integrated circuit device will be described with reference to FIG. 10. As an example, a configuration in which an internal power-supply voltage is generated using two pads PAD1 and PAD2 is shown in FIG. 10.
The conventional power-supply tuning circuit 900 shown in FIG. 10 is provided with power-supply circuits 901 and 902, switching circuits 911 and 912, and NAND circuits 921 and 922.
NAND circuit 921 receives at its inputs a tuning signal applied from pad PAD1 and a pseudo-tuning on signal TUNE. NAND circuit 922 receives at its inputs a tuning signal applied from pad PAD2 and pseudotuning on signal TUNE. Pseudo-tuning on signal TUNE is applied from an external pad PAD0.
Switching circuits 911 and 912 each include power-supply selection transistors N90 and N91. Power-supply selection transistors N90 and N91 in switching circuit 911 switch on/off in response to a control signal S1. Power-supply selection transistors N90 and N91 in switching circuit 912 switch on/off in response to a control signal S2.
Switching circuit 911 supplies the outputs from NAND circuits 921 and 922 to a corresponding power-supply circuit 901 in response to control signal S1. Switching circuit 912 supplies the outputs from NAND circuits 921 and 922 to a corresponding power-supply circuit 902 in response to control signal S2.
When the logic high or xe2x80x9cHxe2x80x9d level pseudo-tuning on signal TUNE is applied from external pad PAD0, power-supply tuning circuit 900 enters a pseudo-tuning mode. In the pseudo-tuning mode, NAND circuits 921 and 922 each output a signal corresponding to a tuning signal applied from outside. Switching circuits 911 and 912 each select a power-supply circuit which perform pseudo-tuning.
Power-supply circuit 901 outputs a voltage in response to the combination of signals (tuning data) received from pads PAD1 and PAD2. The output from power-supply circuit 901 is referred to as an internal power-supply voltage Vref1.
Power-supply circuit 902 outputs a voltage in response to the combination of signals (tuning data) received from pads PAD1 and PAD2. The output from power-supply circuit 902 is referred to as an internal power-supply voltage Vref2.
The configuration of a power-supply circuit included in the conventional power-supply tuning circuit shown in FIG. 10 will be described with reference to FIG. 11. A power-supply circuit 950 shown in FIG. 11 corresponds either of the power-supply circuits 901 and 902 shown in FIG. 10.
Power-supply circuit 950 shown in FIG. 11 includes NMOS transistors 26 and 27, PMOS transistors 21, 22, and 23, and fuses 24 and 25.
Each of the PMOS transistors 21, 22, and 23 is a transistor having a specific resistance value. PMOS transistors 21, 22, and 23 are connected in series between an external power-supply voltage extVCC and a ground potential GND, and the gate electrode of each transistor is connected to ground potential GND.
NMOS transistor 26 and fuse 24 are connected in series between one conductive terminal and the other conductive terminal of PMOS transistor 21. NMOS transistor 27 and fuse 25 are connected in series between one conductive terminal and the other conductive terminal of PMOS transistor 22.
A pseudo-tuning data input node 2a receives an output from NAND circuit 921 shown in FIG. 10. A pseudo-tuning data input node 2b receives an output from NAND circuit 922 shown in FIG. 10.
The gate electrode of NMOS transistor 26 is connected to pseudo-tuning data input node 2a. The gate electrode of NMOS transistor 27 is connected to pseudo-tuning data input node 2b. 
An internal power-supply voltage Vref (corresponding to Vref1 or Vref2 in FIG. 10) is output from a node 2c connecting PMOS transistors 22 and 23. The value of internal power-supply voltage Vref is determined by the ratio of the resistance value between node 2c and ground potential GND with respect to the resistance value between node 2c and external power-supply voltage extVCC.
In the configuration shown in FIG. 11, the resistance value between node 2c and the external power-supply voltage can be selected from four levels by switching on/off each of the NMOS transistors 26 and 27 (or fuses 24 and 25).
In the pseudo-tuning mode (where pseudo-tuning on signal TUNE is activated), each of the NMOS transistors 26 and 27 is switched on/off based on a tuning signal while a fuse is constantly kept ON (fuse is in the connected state). Thus, the states in which the fuse is ON/OFF (connected/disconnected) are emulated. From observed result using a tester, an optimal tuning data (referred to as a tuning code) is determined.
When the internal power-supply voltage is specified for a finished product, NMOS transistors 26 and 27 are kept ON constantly, and fuse 24 or 25 is selectively blown (ON/OFF) by a laser trimmer based on the determined tuning code.
In a conventional power-supply tuning circuit, the same plurality of pads are used to perform pseudo-tuning for a plurality of power-supply circuits, as shown in FIG. 10 and FIG. 11. It is therefore impossible to perform pseudo-tuning simultaneously for a plurality of power-supply circuits.
Consequently, in the conventional pseudo-tuning mode in a wafer test, pseudo-tuning is required for each power-supply circuit in order to determine the optimal tuning code corresponding to each circuit.
In addition, conventionally, it is impossible to set the optimal tuning code for each of the power-supply circuits at the same time. Therefore, in the wafer test, the internal power-supply voltage used is adjusted by applying it from outside.
Moreover, in a conventional power-supply tuning circuit, since the power-supply circuit does not have the current drivability, it is necessary, for example, to tune, to a higher potential, the potential (logic low or xe2x80x9cLxe2x80x9d level) inappropriate to be monitored from outside.
Thus, the present invention provides a semiconductor integrated circuit device which is capable of performing simultaneous pseudo-tuning for a plurality of power-supply circuits.
Moreover, the present invention provides a semiconductor integrated circuit device which can pseudo-tune without the use of a plurality of pads.
Furthermore, the present invention provides a semiconductor integrated circuit device which is capable of performing accurate pseudo-tuning with ease.
The semiconductor integrated circuit device according to an aspect is provided with a plurality of power-supply generation circuits, each including a fuse for generating a desired internal voltage when being blown, a latch circuit for latching tuning data for performing pseudo-tuning, and an emulation circuit for emulating, in response to the data latched by the latch circuit, a blow state of the fuse to emulate outputting of the internal voltage, and a plurality of supply control circuits being disposed corresponding to the plurality of power-supply generation circuits respectively and each controlling supplying of the tuning data to the corresponding power-supply generation circuit.
Thus, one advantage of the present invention is that simultaneous pseudo-tuning for a plurality of power-supply circuits becomes possible with a latch circuit for latching the data for pseudo-tuning provided for each of the plurality of power-supply circuits.
In addition, each power-supply circuit can generate an internal power-supply voltage using the latched data. Therefore, it becomes possible to perform the wafer test using the generated internal power-supply voltage (without applying a voltage from outside).
Particularly, tuning data is automatically generated internally, thus facilitating execution of the test programs. Moreover, since the external pad for applying the tuning data is no longer needed, the chip area can be reduced.
Particularly automatic pseudo-tuning becomes possible when the power-supply tuning circuit enters the test mode.
The tuning code required for generating an appropriate potential is generated internally. Thus, execution of the test programs is facilitated.
Particularly, individual application of the tuning data to a power-supply circuit becomes possible using a power-supply selection transistor.
Particularly, pseudo-tuning becomes possible using a transistor.
Particularly, a fuse blow becomes possible using the data latched by a latch circuit. Thus, a fuse may be blown during the wafer test, reducing the blow time as a result.
The semiconductor integrated circuit device in accordance with the present invention is provided with a power-supply generation circuit including a test mode designating circuit (a circuit for designating a test mode) for detecting the designation of a test mode in response to a test mode designating signal (a signal for designating a test mode) input from outside, a data generation circuit for successively generating tuning data to perform pseudo-tuning in the test mode, a fuse for generating a desired internal voltage when being blown, and an emulation circuit for emulating a blow state of the fuse to emulate outputting the internal voltage.
Another advantage of the present invention is that it becomes possible to perform pseudo-tuning in a test mode by providing a circuit which generates tuning data upon entering the test mode. In addition, since the external pad for applying tuning data is no longer required, the chip area can be reduced.
Particularly, the tuning data is generated by a counter and a ring oscillator which oscillates in the test mode. Thus, the successive generation of tuning data becomes possible in the test mode.
Particularly, since the ring oscillator is also used for self-refresh mode, the chip area can be reduced.
Particularly, a comparator, in particular a current mirror type differential amplifier, for comparing a generated internal power-supply voltage with an appropriate potential is provided. Thus, even when tuning a potential level particularly inappropriate to be monitored (xe2x80x9cLxe2x80x9d level), the tuning state can be monitored by differentially amplifying the difference between the appropriate potential and the xe2x80x9cLxe2x80x9d level potential.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.